1. Field of the Invention
The present invention relates to an output circuit and a synchronous semiconductor memory device which operate in response to a clock signal, and particularly relates to an output circuit and a synchronous semiconductor memory device which can externally transfer data according to accurate timings.
2. Description of the Background Art
In recent years, synchronous DRAMs (which will be referred to as "synchronous semiconductor memory devices" hereinafter) operating in synchronization with a clock signal have been used as main storages for fast MPUs.
A conventional synchronous semiconductor memory device will be described below with reference to FIG. 24. As shown in FIG. 24, a conventional synchronous semiconductor memory device 900 includes a memory cell array 3, an I/O control portion 58, an output portion 50 and a CLKO generating circuit 10.
Memory cell array 3 includes a plurality of memory cells M arranged in rows and columns, a plurality of word lines WL arranged correspondingly to the rows, respectively, and a plurality of bit lines BL arranged correspondingly to the columns, respectively.
CLKO generating circuit 10 is responsive to an external clock signal (which will be referred to as an "external clock signal ext.CLK") sent from an external controller (not shown) to output an output clock CLKO (i.e., a clock for output) controlling an operation of output portion 50 which will be described later. CLKO generating circuit 10 is formed of, e.g., a DLL circuit or a PLL circuit.
I/O control portion 58 transfers externally applied input data to memory cell array 3, and transfers data read from memory cell array 3 to output portion 50. I/O control portion 58 generates an output control signal OEM controlling an output operation of output portion 50. Output portion 50 is responsive to output control signal OEM to transmit output data, which corresponds to the read data, to data I/O terminals DQ0, - - - , DQi (where i is an integer larger than 1).
An operation of I/O control portion 58 shown in FIG. 24 will be described below with reference to timing charts of FIG. 25A-FIG. 25E. As shown in FIGS. 25A-25E, I/O control portion 58 is responsive to a read command READ, which is externally taken in, to generate a control signal OEMF at H-level synchronized with a system clock, i.e., external clock signal ext.CLK (or a clock signal which is an internal signal corresponding to external clock signal ext.CLK). By synchronizing control signal OEMF with output clock signal CLKO, output control signal OEM which is at H-level and therefore active is generated. In a continuous read operation mode, which will be described later, output control signal OEM holds H-level for a period of a length of effective data (i.e., a burst length BL) which is continuously read.
Conventional output portion 50 shown in FIG. 24 will be described below. Conventional output portion 50 has a structure, which is specifically disclosed, for example, in "Data Output Buffer" (Japanese Patent Laying-Open No. 7-262777 (1995)).
An example of the structure of output portion 50 in the prior art will be described below with reference to FIG. 26. FIG. 26 shows an example of a structure of a major portion of conventional output portion 50, and also shows a relationship thereof with respect to OEM generating circuit 52 included in I/O control portion 58.
As shown in FIG. 26, conventional output portion 50 includes a plurality of buffers. FIG. 26 representatively shows output buffers 56.0, 56.1, - - - , 56.15, which will be generally referred to as output buffers 56 hereinafter. Output buffers 56 are connected to corresponding data I/O terminals DQ0, DQ1, - - - , DQ15, respectively, which will be generally referred to as data I/O terminals DQ hereinafter.
Output portion 50 further includes a plurality of latch circuits for transferring read data. FIG. 26 representatively shows, as the latch circuits for read data transfer, latch circuits 54.0, 54.1, - - - , 54.15, which will be generally referred to as data transfer latch circuits 54 hereinafter.
Each of data transfer latch circuit 54 and OEM generating circuit 52 included in I/O control portion 58 is a latch circuit of edge trigger, and takes in a signal, which is received on an input node in, at the falling edge of a signal received on an input node ck. Also, it outputs the signal thus taken at the rising edge of the signal received on input node ck. OEM generating circuit 52 issues output control signal OEM by synchronizing control signal OEMF with output clock signal CLKO.
Output portion 50 is supplied with read data RD(0), RD(1), - - - , RD(15) through data line al. Each data transfer latch circuit 54 receives corresponding read data RD(0), RD(1), - - - , RD(15) on its input, and issues corresponding data DATA(0), DATA(1), - - - , DATA(15), which will be generally referred to as data DATA hereinafter, in response to the rising timing of output clock signal CLKO.
Output buffers 56 receive corresponding data DATA from corresponding data transfer latch circuits 54, and transfer data DOUT (which are represented as DOUT(0), DOUT(l), . . . , DOUT(15) in FIG. 26) to corresponding data I/O terminals DQ based on output control signal OEM, respectively.
A continuous read operation and a continuous write operation in conventional synchronous semiconductor memory device 900 will be briefly described below with reference to timing charts of FIGS. 27A-27F. FIGS. 27A-27F are standard timing charts showing relationships between various signals satisfying the specifications for fast access in conventional synchronous semiconductor memory device 900.
FIGS. 27A-27F are timing charts of the write operation for writing continuous 8-bit data (data of 64(=8.times.8 bits in total), which is read from the memory cells, from each of eight data I/O terminals DQ.
As shown in FIGS. 27A-27F, conventional synchronous semiconductor memory device 900 takes in external control signals (e.g., an external row address signal /RAS and others) as well as an address signal ADD, for example, at the rising edge of external clock signal ext.CLK which is the system clock. As address signal ADD, a row address signal X and a column address signal Y are applied in a time-division multiplexing manner.
At the rising edge of external clock signal ext.CLK, address signal ADD at this point of time is taken in as a row address signal (Xa in FIG. 27) if external row address strobe signal /RAS is active (at L-level), external column address strobe signal /CAS is inactive (at H-level) and external write enable signal /WE is inactive (at H-level).
At the rising edge of external clock signal ext.CLK, address signal ADD at this point of time is taken in as a column address signal (Yb in FIG. 27) if external column address strobe signal /CAS attains the active state (L-level). In accordance with row and column address signals Xa and Yb thus taken, the operation of selecting the row and column in the memory cell array of the synchronous semiconductor memory device is conducted.
When a predetermined clock period (equal to 3 clock cycles in FIG. 27) elapses after external column address strobe signal /CAS falls to L-level, initial 8-bit data (q0 in FIG. 27) is output. A period from the falling of internal column address strobe signal /CAS to L-level to the output of the initial data is called a CAS latency. In FIG. 27, since the data is output after 3 clock cycles, the CAS latency is 3. Thereafter, data q1, - - - , q7 is output in response to the rising of external clock signal ext.CLK so that the data of 64(8.times.8) bits in total is output for 8 clock cycles.
In the continuous read operation, as described above, the access time for the first bit (i.e., the time from rising of external clock signal ext.CLK to actual output of data DOUT) depends on output control signal OEM and output clock signal CLKO, and the data access times for second and subsequent data depend on only output clock signal CLKO.
In the write operation, a row address signal (Xc in FIG. 27) and a column address signal (Yd in FIG. 27) are taken in similarly to the read operation. In response to them, the row and column are selected. Externally applied data (d0 among d0, - - - , d7 in FIG. 27) is taken, as initial write data, into the memory cell corresponding to the selected row and column. As described above, conventional synchronous semiconductor memory device 900 achieves the fast access by performing the continuous reading and continuous writing.
In conventional synchronous semiconductor memory device 900, since a shift occurs in output timing of the data as described above, a failure may occur in an operation of taking in data by an external controller which receives the output data. Brief description will be further given on this problem with reference to FIGS. 28A-28D and 29A-29D.
First, each data transfer latch circuit 54 is arranged immediately before corresponding output buffer 56, and OEM generating circuit 52 generating output control signal OEM is arranged at a position spaced from each output buffer 56. Therefore, the timing with which the output of data transfer latch circuit 54 arrives at output buffer 56 shifts from the timing with which output control signal OEM arrives at output buffer 56.
If output control signal OEM arrives at output buffer 56 before the arrival of data DATA (see FIGS. 28A-28D), invalid data will be output (see the hatched portion in FIG. 28D).
Secondly, in the continuous read operation, the data access time for the first bit depends on output control signal OEM and output clock signal CLKO, but the data access times for second and subsequent bits depend on only output clock signal CLKO.
Therefore, when data DATA arrives at output buffer 56 before output control signal OEM (see FIGS. 29A-29D), a difference occurs between the data access time for the first bit and the data access time for the second bit.
Thirdly, output control signals OEM arrive at output buffers 56 with different timings, respectively, so that a difference (a skew) occurs in access time between data I/O terminals DQ.
As a result, the external controller cannot receive the data according to adequate timing, and cannot reliably perform a correct operation.
Accordingly, an object of the invention is to provide an output circuit which can output data without causing a shift in output timing.
Another object of the invention is to provide a synchronous semiconductor memory device provided with an output circuit which can output data without causing a shift in output timing.
Still another object of the invention is to provide a synchronous semiconductor memory device which allows exact data transfer while suppressing a skew between data I/O terminals.
Yet another object of the invention is to provide a synchronous semiconductor memory device which can minutely adjust a timing of data output independently of an external clock signal.